@koulib@sh.itjust.works to Linux@lemmy.mlEnglish • 2 months agoWhich new Protocol or Standard are you most excited about?message-square53fedilinkarrow-up188arrow-down13file-text
arrow-up185arrow-down1message-squareWhich new Protocol or Standard are you most excited about?@koulib@sh.itjust.works to Linux@lemmy.mlEnglish • 2 months agomessage-square53fedilinkfile-text
minus-squarepizzaboilinkfedilinkEnglish23•2 months agoIs there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.
minus-square@deur@feddit.nllinkfedilink20•edit-22 months agoIn principle it’s just “slimmer ARM”. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports. Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
minus-square@mvirts@lemmy.worldlinkfedilink5•2 months agoI for one think we need a register for each unsigned integer, why is zero so special? :P Or if we can’t get that, at least every power of 2 and power of 2 minus 1. Maybe I can submit a proposal for risc-VI 🤣
minus-square@PetteriPano@lemmy.worldlinkfedilink9•2 months ago Maybe I can submit a proposal for risc-VI 🤣 No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
minus-square@porl@lemmy.worldlinkfedilinkEnglish5•2 months agoI think a register for each of the primes should be enough.
minus-squarecaseyweedermanlinkfedilink3•2 months agoARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
minus-square@MonkderVierte@lemmy.mllinkfedilink3•2 months agoAren’t they more like a hybrid instruction set and architecture?
minus-square☆ Yσɠƚԋσʂ ☆linkfedilink7•edit-22 months agosome good news on that front https://github.com/OpenXiangShan/XiangShan
minus-square@Mwa@lemm.eelinkfedilinkEnglish-3•edit-22 months agoImma stick with ARM and x64 ngl, ik it’s not open hardware but I don’t really mind that but cool to hear.
RISC-V
I want open-source hardware
Is there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.
In principle it’s just “slimmer ARM”. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports.
Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
I for one think we need a register for each unsigned integer, why is zero so special? :P
Or if we can’t get that, at least every power of 2 and power of 2 minus 1.
Maybe I can submit a proposal for risc-VI 🤣
No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
I think a register for each of the primes should be enough.
ARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
Aren’t they more like a hybrid instruction set and architecture?
some good news on that front https://github.com/OpenXiangShan/XiangShan
Imma stick with ARM and x64 ngl, ik it’s not open hardware but I don’t really mind that but cool to hear.